Asymmetrical delay circuits, as shown in FIG. 1, are circuits which exhibit different delays, between the input signal 10 and the output signal 12, for the rising and falling edges of a digital pulse. FIG. 2 shows the timing diagram, depicting the input and output signals, of an example of a prior art asymmetrical delay. As is shown, there is some amount of delay when the input transitions from low-to-high and a different amount of delay when the input transitions from high-to-low. Asymmetrical delay circuits are sometimes used in the address decode circuitry for a memory to ensure the deselection of one memory location before selection of the next memory location. In that application, the asymmetrical delay will also prevent temporary access to an intermediate address when there is some timing skew associated with the individual address bit lines becoming set at slightly different times, if the difference in the time between select and deselect is greater than the amount of skew.
Asymmetrical delay circuits are also used to delay the enabling verses the disabling of a WRITE into a memory so that sufficient time is allowed for establishing access to the correct memory location before enabling of the WRITE.
In a memory, it may be desirable to have a slow select/fast deselect of an addressed cell during WRITE to prevent a temporarily incorrect address from being written into. But during READ, an excessively slow select is not desirable since it directly effects access time.